`timescale 1ns/1ns
`define k 256
`define m 16

module CSA_Tree(input [`k+`m+2:0] a,
				input [`k+`m+2:0] b,
				input [`k+`m+2:0] d,
				input [`k+`m+2:0] e,
				input [`k+`m+2:0] f,
				output [`k+`m+2:0] c,
				output [`k+`m+2:0] s
				);

wire [`k+`m+2:0] c1,c2;

wire [`k+`m+2:0] sum1,sum2;

wire [`k+`m+2:0] c1m,c2m; 

assign c1m = c1 << 1'b1;

assign c2m = c2 << 1'b1;

CSA csa1(.a(a),.b(b),.d(d),.c(c1),.s(sum1));

CSA csa2(.a({c1m}),.b(sum1),.d(e),.c(c2),.s(sum2));

CSA csa3(.a({c2m}),.b(sum2),.d(f),.c(c),.s(s));

endmodule